In the testing of integrated circuits, semiconductor dies or chips are typically tested in wafer form, prior to singulation from the wafer. This testing is often referred to as “wafer testing” or “wafer test.” This is in contrast to, for example, the testing of packaged integrated circuits after singulation and packaging, often referred to as “package testing” or “package test.”
In wafer testing, the semiconductor dies includes contact pads for probing by probes electrically connected to a testing system. Oftentimes, the contact pads are probed multiple times during testing of the wafer to ensure proper contact has been made, particularly in cases where fusing is used in the testing process (e.g., in dynamic random access memory, that is DRAM, devices). The contact pad on the die may not be able to withstand the repetitive probing without sustaining some level of damage or scarring. For example, the contact pad may be damaged so that it is difficult if not impossible to wire bond to the contact pad after singulation from the semiconductor wafer, thereby reducing yield and slowing the wirebonding process. In flip chip applications, the repetitive probing may also reduce yield. Further, the pad may be damaged so that the testing of the semiconductor die is inconclusive as to the viability of the semiconductor die, thereby further reducing yield.
Thus, it would be desirable to provide an apparatus and method for preparing semiconductor dies for wafer test that overcomes one or more of the above-recited deficiencies.